1. Field of the Invention
The present invention relates generally to chip-scale packages and, more specifically, to chip-scale packages which include contact pads on both major surfaces thereof, as well as to methods for forming the chip-scale packages. In particular, the present invention relates to chip-scale packages that include castellated contact pads, which include surfaces, or sections, that are exposed at the outer peripheries of such packages, as well as sections that are exposed at both major surfaces of the packages.
2. Background of Related Art
Conventional semiconductor device packages are typically multi-layered structures. A conventional semiconductor device package may include, for example, a bottom layer of encapsulant material, a carrier, a semiconductor die, and a top layer of encapsulant material. In addition to being located above and beneath the semiconductor die and carrier, the encapsulant material of a conventional semiconductor device package also laterally surrounds the semiconductor device and the carrier. In addition, a conventional semiconductor device package includes input/output elements to facilitate electrical connection of the semiconductor device thereof with external electronic components.
Leads are an example of conventional input/output elements. Leads typically contribute to the dimensions of the footprint of a conventional semiconductor device package and, thus, consume an undesirably large amount of real estate upon a carrier substrate (e.g., a circuit board) to which the semiconductor device package is to be secured and electrically connected.
Other examples of such input/output elements include pins, solder balls or other discrete conductive structures (e.g., bumps, balls, columns, etc.), which contribute to the height of a conventional semiconductor device package. When coupled with the thicknesses that conventional encapsulants and carriers impart to the overall thickness of a conventional semiconductor device package, the added heights of such discrete conductive structures may result in a semiconductor device package which will protrude an undesirably large distance from a carrier substrate to which it is secured and electrically connected.
In order to keep up with the trend toward ever-decreasing the dimensions of electronic devices, various technologies have been developed to decrease the dimensions of packaged semiconductor devices. The result of many of these technologies is the so-called “chip-scale package” (CSP), a packaged semiconductor device with lateral dimensions that are roughly the same as (i.e., slightly larger than) the corresponding lateral dimensions of the semiconductor dice thereof.
Due to the relatively small, semiconductor die-dependent, lateral dimensions of CSPs, they are often formed at the so-called “wafer-scale,” meaning that packaging occurs prior to severing the semiconductor devices from a wafer or other large-scale substrate. Packaging semiconductor devices at the wafer-scale avoids the difficulties that may otherwise be associated with handling such small components during chip-scale packaging thereof. Such wafer-scale packaging may include the formation of a redistribution layer (RDL), which may rearrange or effectively expand the connection pattern of bond pads on the active surface of the semiconductor device to a redistributed connection pattern which is more suitable for connection to a carrier substrate. Alternatively, one or more interposers may be secured over the active surfaces of the semiconductor devices that are carried by a wafer or other large-scale substrate and electrically connected to such semiconductor devices to redistribute the connection patterns thereof.
Once the connection patterns of the semiconductor devices have been redistributed and either before or after the formation of a protective layer over the RDL or interposer, discrete conductive elements, such as balls, bumps, columns, or pins, may be secured to the redistributed bond pads of each CSP. These discrete conductive structures are typically arranged over the major surface in a so-called “grid array” connection pattern.
As a consequence of the use of such discrete conductive structures, chip-scale package technology typically requires inversion of the CSP face-down over a carrier substrate therefor and alignment of the discrete conductive structures of the CSP with corresponding contacts (e.g., the terminals of a circuit board). Electrical connection of a semiconductor device to a carrier substrate in this manner is referred to in the art as “flip-chip” connection or “controlled-collapse chip connection” (C4). Of course, when the discrete conductive structures comprise pins, the electrical connection technique is referred to as a “pin connection.”
When flip-chip or pin connection techniques are employed, the discrete conductive elements typically space the semiconductor device apart from the carrier substrate. This space may remain open or be filled with a so-called “underfill” material. Such spacing of a semiconductor device apart from a carrier substrate may therefore impart the assembly with an undesirably high profile.
Moreover, these types of chip-scale packaging technologies typically do not permit the placement of a chip-scale package on a carrier substrate in a face-up orientation.
Accordingly, there is a need for a packaging technology which results in chip-scale packages that may be secured to carrier substrates without requiring a significant amount of spacing between the chip-scale packages and the carrier substrate and that may be electrically connected to a carrier substrate in a face-up orientation.